Simulink Verification and Validation

Monday, 18 July, 2005 | Supplied by: Ceanet Pty Ltd



MathWorks has announced Simulink Verification and Validation, a product for Simulink that enables system designers and test engineers to perform continuous testing and verification throughout development.

With the new product engineers can now use model-based design to produce a validated executable specification. Through formal testing of systems and algorithms during the modelling and simulation phase, errors can be identified earlier.

The package simplifies the system development workflow by allowing users to link requirements to designs and test cases and perform coverage analysis on Simulink models.

Engineers can ensure that designs are validated earlier in the development process, by identifying inadequate requirements and exposing unnecessary constructs and design flaws at the model level.

It also allows engineers to link their requirements to formal requirements management systems such as Telelogic's Doors, or to Word, Excel, or HTML-formatted files and then navigate back and forth between the requirements and model.

Additionally, users can generate coverage reports to view untested design elements. These reports provide industry standard metrics including RTCA/DO-178B modified condition/decision coverage (MC/DC) and are fully integrated with Simulink.

Metrics can also be displayed in the model, allowing users to quickly traverse the model for missing coverage and navigate to the associated requirements.

In addition to enabling requirements-based design and test of models, Simulink Verification and Validation lets users continue verifying designs throughout the development process.

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